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Researcher Information

last modified:2017/05/23

Professor MATSUDA Yoshio

Mail

Faculty, Affiliation

Faculty of Electrical and Computer Engineering, Institute of Science and Engineering

College and School Educational Field

Division of Electrical Engineering and Computer Science, Graduate School of Natural Science and Technology
Division of Electrical Engineering and Computer Science, Graduate School of Natural Science and Technology
School of Electrical and Computer Engineering, College of Science and Engineering

Laboratory

Multimedia Integrated Circuit System Lab. TEL:076-234-4861 FAX:076-234-4870

Academic Background

Career

Year & Month of Birth

1954/10

Academic Society

Award

○Best Paper Award(2013/03/06)
○Best Paper Award(2013/03/06)
○Best Paper Award(2013/03/06)
○Best Paper Award(2013/03/06)

Specialities

Speciality Keywords

Research Themes

Frame Rate Up Conversion Technology

Motion pictures consist of continuous static image frames that are displayed at a high speed ? dozens of frames per second. Frame-rate up-conversion technology is used for the purpose of motion compensation; it can improve frame rate by interpolating the motion between two adjacent frames and creating adequate in-between frames. We study algorism and architecture for VLSI with the aim of developing a processor to be used exclusively for high-precision real-time frame-rate up-conversion.

Optical Flow Processor

The “optical flow technique” is effective for high-precision recognition of moving images. However, since it recognizes images per pixel, it requires a great deal of calculation, which cannot be processed by software in real time. Thus, we study algorism and architecture for VLSI with the aim of developing a processor that can manage a huge amount of calculation of optical flow.

Advanced SRAM and Memory Based LSI

We aim to improve the performance of state-of-the-art fine-cell SRAM and its fundamental properties such as fluctuation tolerance, and develop a new functional LSI based on CAM and SRAM.

Books

  •  A VGA 30 fps Affine Motion Estimation Processor for Real-Time Video Segmentation 2008/08
  •  A 158 MS/s JPEG 2000 Codec with a Bit-plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission 2008/08
  •  A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition 2008/04

Papers

  •  A Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications 2008 12 253-2256 2008/11
  •  A Short Stub-Matching 77-GHz-Band Driver Amplifier with an Attenuater Compensating Temperature Dependence of a Gain 2005
  •  Adiabatic SRAM with a large margin of VT variation by decreasing the power line during writing and using a verifying operation during reading 2009 05 393 - 396 2009/05
  •  A VLSI Architecture for VGA 30 fps Video Segmentation with Affine Motion Model Estimation 2009 12 2009/12
  •  A VGA 30 fps Affine Motion Estimation Processor for Real-time Video Segmentation E93-D 12 3284-3292 2010/12

show all

  •  A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications E93-C 5 685-695 2010/05
  •  Simultaneous Enlargement of SRAM Read/Write Noise Margin by Controlling Virtual Ground Lines 2010 6 73-76 2010/06
  •  FPGA Implementation of Fast Optical Flow Algorithm with Robustness for Luminance Chang 40 1 191 2011/01
  •  Reexamination of SRAM cell write margin definitions in view op predicting the distribution 58 4 230-234 2011/04
  •  An adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system 4 4 301-311 2010/08
  •  VGA 131 fps Affine Motion Model Estimation VLSI Processor J94-D 12 2082-2092 2011/12
  •  Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation 7 9 640-646 2010/07
  •  A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance Nakata, Shunji; Makino, Hiroshi; Matsuda, Yoshio Midwest Symposium on Circuits and Systems 439-442 2014/01/01 
  •  Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution Makino, Hiroshi;Nakata, Shunji;Suzuki, Hirotsugu;Mutoh, Shin'ichiro;Miyama, Masayuki;Yoshimura, Tsutomu;Iwade, Shuhei;Matsuda, Yoshio IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 58 4 230-234 2011
  •  Automatic Rule Registration and Deletion Function on a Packet Lookup Engine LSI T. Matsumura, K. Imamura, Y. Kawamura, and Y. Matsuda IEEE ISPACS 34-39 2016/10
  •  Image Denoising using Non-local Means for Poisson Noise K. Imamura, N. Kimura, F. Satou, S. Sanada and Y. Matsuda IEEE ISPACS 7-12 2016/10
  •  A Study on Motion Estimation Algorithm for Moving Pictures R. Bandou, M. Hiramori, S. Iwade, H. Makino, T. Yoshimura, and Y. Matsuda IEEE GCCE 352-354 2016/10
  •  A Study on Motion Estimation Algorithm M. Hiramori, R. Bandou, S. Iwade, H. Makino, T. Yoshimura, and Yoshio Matsuda IEEE GCCE 349-351 2016/10
  •  A Fast Atom Selection Method Based on the Order of Initial Inner Product Values for Image Denoising Using Sparse Representation K. Imamura, K. Itoh, and Y. Matsuda IEEE ISPACS 188-193 2015/11
  •  A 100-MHz 51.2-Gb/s Packet Lookup Engine LSI Based on Mismatch Detection Circuit Combined with Linked-List Hash Table Y. Kawamura, K. Imamura, N. Miura, M. Urano, S. Shigematsu, and Y. Matsuda IEEE ISPACS 351-356 2015/11
  •  A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm T. Matsumura, A. Kurokawa, K. Imamura, and Y. Matsuda IEEE DDECS 31-36 2015/04
  •  A New Stepwise Adiabatic Charging Circuit with a Smaller Capacitance in a Regenerator than a Load Capacitance S. Nakata, H. Makino, and Y. Matsuda IEEE MWSCAS 439-442 2014/08
  •  Estimation of Threshold Voltage from Frequency of Ring Oscillator T. Matsumoto, H. Makino, T. Yoshimura, S. Iwade, and Y. Matsuda IEEE IMFEDK 104-105 2014/06
  •  The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals T. Matsumura, N. Okada, Y. Kawamura, K. Nii, K. Arimoto, H. Makino, and Y. Matsuda IEEE DDECS 183-188 2014/04
  •  A 96.5% Energy-Reduced Lookup Engine with an Unused-Rules-Exception Scheme for Greening Networks N. Miura, R. Honda, S. Shigematsu, N. Tanaka, S. Hatta, M. Nakanishi, Y. Matsuda, and M. Urano Symposium on VLSI Circuits C288-C289 2013/06
  •  Expansion of SRAM Operation Margin by Adaptive Voltage Supply K. Kishida, T. Tsujii, H. Makino, T. Yoshimura, S. Iwade, and Y. Matsuda IEEE IMFEDK 104-105 2013/06
  •  A Cost-Effective 45nm 6T-SRAM Reducing 50mV Vmin and 53% Standby Leakage with Multi-Vt Asymmetric Halo MOS and Write Assist Circuitry K. Nii, M. Yabuuchi, H. Fujiwara, Y. Tsukamoto, Y. Ishii, T. Matsumura, Y. Matsuda IEEE ISQED 438-441 2013/03
  •  The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals T. Matsumura, N. Okada, Y. Kawamura, K. Nii, K. Arimoto, H. Makino, and Y. Matsuda IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS),  183-188 2014/04
  •  A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals Y. Kawamura, N. Okada, Y. Matsuda, T. Matsumura, H. Makino, K. Arimoto IEICE TRANS. INF. & SYST E99-A 5 917-928 2016/05
  •  Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of Its Duty Ratio Nakata, H. Makino, J. Hosokawa, T. Yoshimura, S. Iwade, Y. Matsuda IEEE Transactions on Circuits and Systems I 61 2194-2230 2014/07
  •  Analysis of Voltage, Current, and Energy Dissipation of Stepwise Adiabatic Charging of a Capacitor Using a Nonresonant Inductor Curren S. Nakata, H. Makino, R. Honda, M. Miyama, Y. Matsuda Journal of Circuits, Systems, and Computers 23 3 21 pqges 2014/03
  •  Increase in Read Noise Margin of Single-bit-line SRAM using Adiabatic Change of Word Line Voltage for Low- Power Applications S. Nakata, H. Hanazono, H. Makino, H. Morimura, M. Miyama, Y. Matsuda IEEE Transactions on VLSI Systems 22 3 686-690 2014/03
  •  Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-locked Loop T. Yoshimura, S. Iwade, H. Makino, and Y. Matsuda IEEE Transactions on Circuits and Systems I: 60 4 896-907 2013/04
  •  Utilizing the Normal Distribution of the Write Noise Margin to Easily Predict the SRAM Write Yield H. Makino, S. Nakata, H. Suzuki, S. Mutoh, M. Miyama, T. Yoshimura, S. Iwade, Y. Matsuda IET Circuits, Devices & Systems 6 4 260-270 2012/10
  •  General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit with Any Circuit Topology S. Nakata, R. Honda, H. Makino, S. Mutoh, M. Miyama, Y. Matsuda IEEE Transactions on Circuits and Systems I: 59 10 2301-2314 2012/10

Conference Presentations

Arts and Fieldwork

Patent

Theme to the desired joint research

Grant-in-Aid for Scientific Research

Classes (Bachelors)

○Microelectronics 1(2017)
○Student-Initiated Project(2017)
○Computer System(2017)
○Microelectronics II(2017)
○Microelectronics II(2016)
○Computer System(2016)
○Student-Initiated Project(2016)
○Microelectronics 1(2016)

Classes (Graduate Schools)

○VLSI Multimedia Processor(2017)
○VLSI Multimedia Processor(2017)
○VLSI Multimedia Processor(2017)
○VLSI Multimedia Processor(2017)
○Advanced Integrated Circuits Technology(2017)
○VLSI Multimedia Processor(2016)

International Project

International Students

Lecture themes

Others (Social Activities)

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